1. Field of the Invention
The present invention relates to a high-voltage metal-oxide-semiconductor (HV MOS) transistor device and manufacturing method thereof, and more particularly, to a HV MOS transistor device for reducing parasitic capacitance and a manufacturing method thereof.
2. Description of the Prior Art
Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operation voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low doping concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, and therefore LDMOS transistor device can have higher breakdown voltage. In a drain extending MOS (DEMOS) transistor, the drift region is disposed between the gate and the drain, and the parasitic capacitance between gate and drain will affect the operation of the device. For example, when the DEMOS transistor is used as a power amplifier, the power added efficiency (PAE) will be lowered by larger gate-to-drain parasitic capacitance (Cgd), and the Cgd has to be reduced by modifying structural designs.